1. Technical Field
This disclosure relates to a semiconductor memory device, and more particularly to a serializer and a method of converting parallel data with a low frequency into serial data with a high frequency.
2. Description of the Related Art
Generally, a high-speed transfer mode converting low-speed parallel data into high-speed serial data is used in network systems in order to transfer data at high speeds.
In a memory system, a parallel bus structure that has a wide bandwidth is typically used as a bus structure between a processor and a semiconductor memory in order to transfer a large amount of data. Since an operating speed of a semiconductor memory is lower than that of a processor, a processing speed of the entire memory system is also low.
A bus system having a wider bandwidth is needed in order to increase a processing speed between a processor and a semiconductor memory while maintaining an operating speed of the semiconductor memory. As a bandwidth becomes wider, the number of input/output (I/O) pins of a semiconductor memory device is also increased, sometimes by as much as hundreds of pins. Thus, a cost of a semiconductor memory device may be increased. High numbers of I/O pins are needed for high speed, high capacity and high performance, and thus manufacturing costs may be increased.
Therefore, in the field of semiconductor memory, active research on data serializing technologies that convert parallel data into serial data is being conducted in order to increase data transfer speeds between a memory and a processor.
A data serializing device in a semiconductor memory device is manufactured by complementary metal-oxide semiconductor (CMOS) circuit design technologies.
In a semiconductor memory device, a CMOS circuit technology is used in converting eight bits of parallel data having a differential form into ten bits of serial data. Ten branch circuits that respectively include one p-type MOS (PMOS) transistor as a pull-up device and one n-type MOS (NMOS) transistor as a pull-down device are coupled to an output node. When input data corresponds to a logic high, a voltage of the output node becomes a logic low rapidly through the branch circuits including NMOS transistors. However, when input data corresponds to a logic low, a voltage of the output node becomes a logic high relatively slowly because large parasitic capacitances generated from the ten branch circuits are charged by one small PMOS transistor. Imbalance between a rising transition time and a falling transition time at the output node causes a skew so that a data transfer speed may be decreased.
For a semiconductor memory device, a method for diminishing parasitic capacitances includes reducing the number of pull-down devices connected to an output node by half to raise a pull-up speed.
For a semiconductor memory device, another method of balancing between pull-up characteristics and pull-down characteristics at an output node equalizes the number of pull-up devices and pull-down devices.
FIG. 1 is a circuit diagram illustrating a conventional serializer.
Referring to FIG. 1, the serializer includes PMOS transistor MP1 between a supply voltage VDD and an output node N0. A gate of the PMOS transistor MP1 is provided with a bias voltage Vb. A voltage of the output node N0 is pulled up by the bias voltage Vb through the PMOS transistor MP1 with a predetermined current driving capability.
Four pull-down circuits PDC1, PDC2, PDC3 and PDC4 are coupled in parallel between the output node N0 and a ground voltage VSS. A first pull-down circuit PDC1 includes serially coupled NMOS transistors MN1, MN2 and MN3. A first clock signal CLK1 is applied to a gate of the NMOS transistor MN1, a second clock signal CLK2 is applied to a gate of the NMOS transistor MN2, and first input data IN1 is applied to a gate of the NMOS transistor MN3. A second pull-down circuit PDC2 includes serially coupled NMOS transistors MN4, MN5 and MN6. The second clock signal CLK2 is applied to a gate of the NMOS transistor MN4, a third clock signal CLK3 is applied to a gate of the NMOS transistor MN5, and second input data IN2 is applied to a gate of the NMOS transistor MN6. A third pull-down circuit PDC3 includes serially coupled NMOS transistors MN7, MN8 and MN9. The third clock signal CLK3 is applied to a gate of the NMOS transistor MN7, a fourth clock signal CLK4 is applied to a gate of the NMOS transistor MN8, and third input data IN3 is applied to a gate of the NMOS transistor MN9. A fourth pull-down circuit PDC4 includes serially coupled NMOS transistors MN10, MN11 and MN12. The fourth clock signal CLK4 is applied to a gate of the NMOS transistor MN10, the first clock signal CLK1 is applied to a gate of the NMOS transistor MN11, and fourth input data IN4 is applied to a gate of the NMOS transistor MN12. The NMOS transistors MN1 through MN12 are manufactured to have a higher current driving capability with respect to the PMOS transistor MP1.
FIG. 2 is a timing diagram illustrating operations of the serializer in FIG. 1.
Referring to FIG. 2, each of the four clock signals CLK1, CLK2, CLK3 and CLK4 have identical periods and are 90 degrees out of phase with each other. A phase of the second clock signal CLK2 is delayed as much as 90 degrees with respect to that of the first clock signal CLK1, a phase of the third clock signal CLK3 is delayed as much as 90 degrees with respect to that of the second clock signal CLK2, and a phase of the fourth clock signal CLK4 is delayed as much as 90 degrees with respect to that of the third clock signal CLK3. The first input data IN1 is synchronized with a rising edge of the first clock signal CLK1, the second input data IN2 is synchronized with a rising edge of the second clock signal CLK2, the third input data IN3 is synchronized with a rising edge of the third clock signal CLK3, and the fourth input data IN4 is synchronized with a rising edge of the fourth clock signal CLK4.
The first input data IN1 is transferred to the output node N0 while the first and second clock signals CLK1 and CLK2 are turned on, the second input data IN2 is transferred to the output node N0 while the second and third clock signals CLK2 and CLK3 are turned on, the third input data IN3 is transferred to the output node N0 while the third and fourth clock signals CLK3 and CLK4 are turned on, and the fourth input data IN4 is transferred to the output node N0 while the fourth and first clock signals CLK4 and CLK1 are turned on.
Thus, when input data is a logic high, although the PMOS transistor MP1 is turned on, one of the pull-down circuits PDC1, PDC2, PDC3 and PDC4 including the NMOS transistors, which have higher current driving capability with respect to the PMOS transistor MP1, is turned on so that the voltage of the output node N0 is pulled down to the ground voltage VSS in synchronization with the clock signal.
However, when input data is a logic low, although one of the pull-down circuits PDC1, PDC2, PDC3 and PDC4 is selected by the clock signal, the pull-down circuits PDC1, PDC2, PDC3 and PDC4 are turned off so that the voltage of the output node N0 is pulled up only by the PMOS transistor MP1 that is turned on.
As a result, a rising transition time may be longer than a falling transition time at the output node N0. In addition, a falling edge is synchronized with the clock signal, but a rising edge is not synchronized with the clock signal. Imbalance between a rising transition time and a falling transition time of serialized data may cause data skew.